1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to circuit devices incorporating dislocation regions for charge neutralization and to methods of making the same.
2. Description of the Related Art
Integrated circuit fabrication on semiconductor-on-insulator (“SOI”) substrates holds the promise of significant device scaling through increased packing density. In complimentary metal oxide semiconductor (“CMOS”) circuit designs, SOI eliminates some latch-up issues normally present in CMOS design rules. In SOI substrates, junction isolation is provided by surrounding active device regions with an insulator. A typical SOI substrate includes a plurality of silicon islands formed on an insulating layer, usually of oxide. The silicon islands are also isolated laterally by an insulator, again usually an oxide.
Device fabrication on SOI substrates is similar in many respects to conventional device fabrication on conventional semiconductor substrates in which device isolation is provided by trench isolation or field oxide regions and impurity wells. For example, one conventional technique for field effect transistor fabrication on a SOI substrate entails gate dielectric layer and gate electrode fabrication followed by a self-aligned lightly doped drain (“LDD”) implant and a source/drain implant. Spacers may be applied to provide lateral set-off of the impurity regions.
In some conventional processes tailored for device isolation via impurity wells and isolation trenches, an amorphization implant is performed following gate electrode formation but prior to source/drain region implants. The goal of the amorphization implant is to establish surface amorphous regions that are self-aligned to the gate electrode. The surface level amorphous regions make the upper reaches of the device region resistant to ionic channeling during ion implantation. The subsequently-performed LDD implant will exhibit little ionic channeling and produce a relatively shallow p-n junction. The amorphous regions are later recrystallized during an anneal step.
One technical hurdle associated with SOI device fabrication is associated with floating body effects. In a conventional substrate wherein device isolation is provided by isolation trenches and impurity wells, the body of a transistor is coupled electrically to the remainder of the substrate. However, in a SOI substrate, the body of the device is floating. As a consequence, charge can accumulate in the body. The amount and rate of charge accumulation are dependent upon a number of factors, such as the number of times of the transistor is switched on and off and the geometry of the transistor and the device region, to name a few. Accumulated charge in the body can lead to undesirable variances in the switching speed of the transistor. The problem of floating body effects is generally more acute for partially depleted devices, such as partially depleted field effect transistors, than for fully depleted devices.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.